This invention relates to digital video systems which send multiple streams of video data from a video library to respective sets of viewers. In the prior art, one such system is described in U.S. Pat. No. 5,583,561 which is entitled xe2x80x9cMulti-Cast Digital Video Server Using Synchronization Groupsxe2x80x9d.
An overview of the above prior art system is shown in FIG. 1 of patent ""561. There, multiple video programs are stored in a video library 10 which is coupled to a video server 12; and, the video server 12 is coupled through a network interface circuit 18 and a distribution network 20 to a plurality of addressable display devices 22, 24, and 26. To receive a particular video program at a particular display device, a request is sent by a viewer via a telephone to the video server.
A primary feature of patent ""561 is that as the requests for the video programs are randomly received by he video server, they are partitioned into a redetermined number of synchronization groups. This is shown in FIGS. 5, 6A and 6B of patent ""561. One synchronization group consists of the requests for a video program that are received between time T0 and T1; the next synchronization group consists of the requests for the same video program which are received between time T1 and T2; etc.
All of the viewers in a particular synchronization group are sent the requested video program starting at the same time; and each such transmission of the video program is called a xe2x80x9cstreamxe2x80x9d. In FIG. 5, the transmission of a video program which begins at time T0 is called STREAM #1; the transmission of the same program which begins at time T1 is called STREAM #2; etc.
By utilizing the synchronization groups and their respective streams, the total number of times which a video program must be transmitted from the video library 10 to the video server 12 is greatly reduced. Only one such transmission occurs for each synchronization group. By comparison without the synchronization groups, the video program must be transmitted from the video library each time a request for the program is received. Similarly, the synchronization groups reduce the total number of times which a video program must be transmitted from the video server 12 to the network interface circuit 18.
However, a drawback of the video system in patent ""561 is that the network interface circuit 18 is comprised of an I/O processor 48, a multi-cast interface circuit 50, and an ATM interface 52; and, all three of those items must be replicated for each video stream that is sent concurrently with other video streams to the viewers. This is shown in FIGS. 2, 3, and 7.
For example, FIG. 2 shows the I/O processor 48 and the multi-cast circuit 50 and the ATM interface circuit 52 within the network interface 18. Further, FIG. 7 shows that each multi-cast interface circuit includes a single pair of frame buffers 90 and 92 which store portions of one video stream, a single pair of destination lists 94 and 98 which identify the viewers for the video stream that is in the frame buffers 90 and 92, and a control circuit 96. In operation, the control circuit 96 determines when and where the stored portion of the single video stream is sent from the frame buffers, and determines when the frame buffers need to be written with another portion of the video stream.
In FIG. 7 of patent""561, the control circuit 96 is simply shown as a labeled box. However, to actually control when and where the stored portion of the video stream is sent, and control when the frame buffers are updated, is a complex operation which by itself requires a substantial amount of circuitry to implement. Consequently, when all of the circuitry within items 48, 50, and 52 is duplicated for each video stream that is sent concurrently with others to the viewers, then the total cost of the resulting system can be too high to be competitive in the marketplace.
Accordingly, a primary object of the present invention is to provide an improved digital video system which avoids the above problem.
In accordance with the present invention, a video system is comprised of the following components: a) a single supervisor processor, and multiple co-processors which are selectable in number and are coupled via a bus to the single supervisor processor; b) a supervisor memory which is coupled to the supervisor processor and which stores a respective portion of each of several video streams; c) a control program in each co-processor which selectively reads the stored video stream portions from the supervisor memory and sends each video stream portion that is read to a different viewer; and d) a control program for the single supervisor processor, which dynamically updates the stored portion of each video stream in the supervisor memory and which services external requests to change the respective viewers of each video stream.
One particular feature of the above video system is that it is highly scalable and economical. This feature is achieved because the number of co-processors is selectable; the number of video streams which are sent by each co-processor is selectable; and, the number of viewers per stream is selectable. By making these selections, the system can be increased or decreased in size to meet the different requirements of many customers. Further, since the system includes only a single supervisor processor and a single supervisor memory which operate in a shared fashion with all of the co-processors, the cost of those items is incurred only once.
With the above video system, each co-processor can send different video streams to respective lists of viewers; and in addition, a group of two or more co-processors can send the same video stream to respective lists of viewers. In one embodiment, the co-processors in the group run asynchronously, and the stored portion of that same video stream is duplicated for each co-processor in the group. In a second embodiment, the co-processors in the group run asynchronously, and a single portion of that same video stream is stored in three consecutive subparts which are shared by all of the co-processors in the group. In a third embodiment, a synchronizer circuit is provided for the co-processors, and a single portion of that same video stream is stored in two sub-parts which are shared by all of the co-processors in the group.